一种消除采样频偏的定时同步架构  

A timing synchronization architecture for eliminating sampling frequency bias

作　　者：肖磊 张宴槐 李浩[2] 李旭阳 别智恒 卫洋斌 XIAO Lei;ZHANG Yanhuai;LI Hao;LI Xuyang;BIE Zhiheng;WEI Yangbin(CETC Key Laboratory of Avionic Information System Technology,Chengdu 610036,China;School of Automation Engineering,University of Electronic Science and Technology of China,Chengdu 611731,China)

机构地区：[1]中国电子科技集团公司航空电子信息系统技术重点实验室,四川成都610036 [2]电子科技大学自动化工程学院,四川成都611731

出　　处：《微电子学与计算机》2024年第12期51-59,共9页Microelectronics & Computer

基　　金：国家自然科学基金(62303091);中国博士后面上基金(2021M700707);四川省自然科学基金(2022NSFSC0905)。

摘　　要：针对传统定时同步技术难以满足高速率通信传输的问题,基于任意分数倍重采样提出了一种适用于硬件平台实现的可消除采样频偏的并行定时同步架构,包括定时相偏反馈校正环路和采样频偏前馈校正环路。具体地,定时相偏反馈校正环路采用数字平方滤波法实现;采样频偏前馈校正环路采用滑动窗口实现。首先,通过任意倍率重采样对采样频偏进行粗调;然后通过采样频偏校正模块完成采样频偏的细调。其次,通过理论推导和分析,给出了定时同步架构中各个模块的并行FPGA实现架构。最后,针对800 MHz载波频率、1×10^(8) symbol/s符号率的QPSK信号,对提出的并行联合定时同步架构进行了硬件仿真验证。结果表明:该定时同步架构可以有效消除采样频偏,硬件输出结果与MATLAB无采样频偏的仿真结果基本保持一致。Aiming at the problem that traditional timing synchronization technology is difficult to meet the high speed communication transmission,this paper proposes a timing synchronization architecture based on arbitrary fraction double resampling to eliminate sampling frequency bias,which can be implemented in FPGA hardware platform through algorithmlevel pipelined parallel.The proposed timing synchronization architecture includes timing feedback correction loop and sampling frequency bias feedforward correction loop.Specifically,the timing feedback correction loop is implemented by digital square filter.Sampling frequency offset feedforward correction loop is implemented by sliding window.Firstly,the sampling frequency offset is coarse adjusted by resampling at arbitrary rate,and then the sampling frequency offset correction module is used to complete the fine adjustment of sampling frequency offset.Secondly,through theoretical derivation and analysis,this paper gives the parallel FPGA implementation architecture of each module in timing synchronization architecture.Finally,QPSK signals with 800 MHz carrier frequency and 1×10^(8) symbol/s symbol rate are set in MATLAB and FPGA platforms.The proposed parallel joint timing synchronization architecture is simulated and verified in this paper.The results show that the timing synchronization architecture can make the output result consistent with the ideal non-sampling frequency deviation in MATLAB simulation by eliminating the sampling frequency deviation.

关 键 词：定时同步 采样时钟偏移 数字滤波平方 重采样 FPGA实现 

分 类 号：TN927.21[电子电信—通信与信息系统]