Au/BIT/PZT/BIT/p-Si(100)存储器  

The Au/BIT/PZT/BIT/p-Si(100) Memory

作　　者：李兴教[1] 王宁章[1] 鲍军波[1] 宁广蓉[1] 陈涛[1] 徐静平[1] 陈振贤[1] 邹雪城[1] LI Shao-ping 

机构地区：[1]华中科技大学电子系,武汉430074 [2]Advanced Recording Technology Laboratory,Seagate Technology

出　　处：《压电与声光》2002年第6期440-444,共5页Piezoelectrics & Acoustooptics

基　　金：国家自然科学基金资助项目(59972010)。

摘　　要：利用准分子激光原位淀积方法制备了BIT/PZT/BIT,PZT/BIT和BIT层状铁电薄膜,获得了电流密度-电压(I-V)回线和极化强度P-V电滞回线。在这三种结构中,Au/BIT/PZT/BIT/p-Si(100)结构的界面电位降、内建电压及频率效应是最小的。在电压转变电VT、饱和极化强度PS及矫顽场VC之间有三种关系,他们与I-V回线及P-V回线的关系相匹配,这种匹配关系使得以I-V回线操作的存储器将能够非挥发和非破坏读出及具有保持力。Multiplayer ferroelectric thin films BIT/PZT/BIT,PZT/BIT and BIT were deposited on (100) ptype silicon wafers by pulsed excimer laser.IV loop and PV loop were obtained.Among three structures,the voltage drop and built in voltage anad frequency effect at the interface of Au/BIT/PZT/BIT/pSi(100) is the smallest.There are three relations between VT,Ps and Vc,which are the conditions of the match relation between IV loop and PV loop,which maintains that this memory operated IV loop will enable nonvolatile memory,nondestructive readout and retention.

关 键 词：Au/BIT/PZT/BIT/p-Si(100) 存储器 铁电薄膜 电位降 内建电压 金属/铁电薄膜/半导体 结构 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]