定时系统的VHDL设计  

Design of Timing System Using VHDL

作　　者：何广军[1] 戴庆元[1] 

机构地区：[1]上海交通大学微电子技术研究所,上海200052

出　　处：《计算机工程》2002年第12期227-229,共3页Computer Engineering

摘　　要：用VHDL硬件描述语言设计定时系统，定时采用时钟控制，并用Mealy有限状态机表示定时器的状态，并考虑了控制器的微程序设计实现，然后用VHDL进行了描述，并给出了主要部分的模拟结果。A timin system is described using VHDL in this article,the time to be delayed can be controlled by adjusting the frequenct of the clock,which can also be done by setting the frequency divider.FSM of Meally is adapoted to set the state of the timing system,and the mothod of microprogramming is described.At the end of the article,the flow chart is given and simulation result is attached.

关 键 词：定时系统 VHDL 设计 有限状态机 硬件描述语言 微程序设计 

分 类 号：TP311.1[自动化与计算机技术—计算机软件与理论]