基于FPGA的高精度时间数字转换器设计与实现  

Design and Realization of High-Precision Time to Digital Converter Based on FPGA

作　　者：项圣文 包朝伟 蒋伟 唐万韬 XIANG Shengwen;BAO Chaowei;JIANG Wei;TANG Wantao(Shenzhen Pango Microsystems Co.,Ltd.,Shenzhen 518000,China)

机构地区：[1]深圳市紫光同创电子有限公司,广东深圳518000

出　　处：《电子与封装》2025年第1期35-41,共7页Electronics & Packaging

基　　金：深圳市技术攻关重点项目:重2022D006国产化高性能工业机器人控制器研发及应用(JSGGZD20220822095000001)。

摘　　要：高精度时间间隔测量是激光测距、雷达、示波器等多种科学和工程领域中的关键技术。为了提高测量的精确度,使用FPGA器件抽头延迟链实现高精度时间数字转换器(TDC),通过脉冲计数法和抽头延迟线法实现完整时钟周期和非完整时钟周期的测量,并提出一种使用锁相环(PLL)动态调相功能测量延迟链精度的方法,PLL调相精度为15.625 ps,通过多级延迟链级联取平均值的方式减小PLL调相精度引入的测量误差,最小测量误差为0.3125 ps。以紫光同创Logos2系列FPGA芯片实现TDC的设计,仿真验证和板级测试结果证明,使用50级延迟链能实现非完整时钟周期的测量,测量精度为71 ps,TDC时间间隔测量范围小于4.2950 ms。High-precision time interval measurement is a key technology in various scientific and engineering fields such as laser ranging,radar,and oscilloscopes.In order to improve the accuracy of the measurements,an FPGA tap delay chain is used to implement a high-precision time to digital converter(TDC).Measurements of complete and incomplete clock cycles are achieved through pulse counting and tap delay line methods.A method is proposed to measure the delay chain accuracy using phase locked loop(PLL)dynamic phase modulation function,with a PLL phase modulation accuracy of 15.625 ps.The measurement error introduced by PLL phase modulation accuracy is reduced by averaging over multiple delay chain cascades,with a minimum measurement error of 0.3125 ps.The design of TDC is achieved using the Pango Logos2 series FPGA chip,the simulation verification and board-level test results prove that the measurement of incomplete clock cycles is achieved using a 50-level delay chain,with a measurement accuracy of 71 ps,and the measurement range of TDC time interval is less than 4.2950 ms.

关 键 词：时间数字转换器 高精度 FPGA 进位链 抽头延迟线 

分 类 号：TN791[电子电信—电路与系统]