多核微处理器EDAC与位交织加固存储系统单粒子翻转特性分析  

Characterization of single-event upset in the EDAC and bit-interleaving hardened storage system of the multicore microprocessor

作　　者：池雅庆[1,2] 胡春媚[1,2] 陈建军[1,2] 梁斌[1,2] 陈小文[1,2] CHI Yaqing;HU Chunmei;CHEN Jianjun;LIANG Bin;CHEN Xiaowen(School of Computing,National University of Defense Technology,Changsha 410073,China;Key Laboratory of Advanced Microprocessor Chips and Systems,National University of Defense Technology,Changsha 410073,China)

机构地区：[1]国防科技大学计算机学院,湖南长沙410073 [2]国防科技大学先进微处理器芯片与系统教育部重点实验室,湖南长沙410073

出　　处：《微电子学与计算机》2025年第1期110-116,共7页Microelectronics & Computer

基　　金：国家自然科学基金(62174180)。

摘　　要：纠检错结合位交织作为主流的大容量片上存储器抗单粒子翻转加固方法,广泛应用于面向恶劣环境的先进微处理器中。基于高LET重离子辐照试验,探究某多核微处理器中EDAC与位交织加固存储系统的单粒子翻转特性,首次发现其SEU来源于加速器重离子试验时多个离子轰击造成的多位翻转影响到了同一个逻辑地址。建立了纠一检二与位交织存储系统SEU截面解析模型,符合测试结果。模型分析表明缩短SRAM刷新周期和减少EDAC数据位宽都能增强EDAC和位交织加固方法的抗MBU能力。EDAC(Error Detection and Correction)combining with bit-interleaving is the domestic single-event upset hardening method for the large-capacity on-chip memories,widely used in advanced microprocessors for harsh environments.Based on the high LET heavy ion radiation test,the single-event upset effect is studied in the EDAC and bitinterleaving hardened storage systems of a multicore microprocessor.The mechanism of the SEU is found for the first time,which is attributed to the influence of multi-bits upsets caused by multiple heavy ions on the same logical address.A compact model of the SEU cross-section is proposed for the SEC-DED(Single Error Correct/Double Error Detect)and bitinterleaving hardening storage system,which is consistent with the test results.Reducing the SRAM refresh period and the EDAC bit width data can enhance the MBU resistance of the EDAC and bit interleaving hardening method.

关 键 词：EDAC SEC-DED 位交织 单粒子翻转 SRAM 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]