基于FPGA的JPEG-XS高性能解码器硬件架构设计  

Design of a High-Performance JPEG-XS Decoder Hardware Architecture Based on FPGA

作　　者：郑畅 吴林煌[1] 李雅欣 刘伟 ZHENG Chang;WU Linhuang;LI Yaxin;LIU Wei(College of Physics and Information Engineering,Fuzhou University,Fuzhou 350108,China)

机构地区：[1]福州大学物理与信息工程学院,福州350108

出　　处：《电子与封装》2025年第2期49-54,共6页Electronics & Packaging

摘　　要：JPEG-XS视频编解码标准具有高质量、低复杂度、低延时等特点。针对JPEG-XS图像编解码压缩标准,对其解码算法进行了简要介绍,提出了一种面向硬件实现的高性能JPEG-XS解码器架构。所设计的解码器硬件架构采用流水线处理,能够在保持高数据吞吐量的同时减少由组合逻辑带来的路径延迟,提高了工作频率,每个时钟周期可解码4个重构像素值。实验结果表明,在Xilinx Zynq FPGA的实验平台上,所设计的高性能JPEG-XS解码器硬件架构仅占用约15×103个查找表和11×103个寄存器资源,最高主频达254 MHz,最高可支持4K、100帧/s的实时视频解码。JPEG-XS video codec standard is characterized by high quality,low complexity and low latency.Aiming at the JPEG-XS image codec compression standard,its decoding algorithm is briefly introduced,and a high-performance JPEG-XS decoder architecture oriented to hardware implementation is proposed.The designed decoder hardware architecture adopts pipelined processing,which is able to reduce the path delay caused by combinational logic while maintaining a high data throughput,increase the operating frequency,and decode four reconstructed pixel values per clock cycle.The experimental results show that the designed high-performance JPEG-XS decoder hardware architecture occupies only 15×103 look-up tables and 11×103 register resources on the experimental platform of Xilinx Zynq FPGA,with a maximum main frequency of 254 MHz,and can support up to 4K and 100 frame/s real-time video decoding.

关 键 词：JPEG-XS 解码器 FPGA 视觉无损 硬件架构 

分 类 号：TN402[电子电信—微电子学与固体电子学] TP391.4[自动化与计算机技术—计算机应用技术]