一种基于节点冗余技术的低功耗容忍DNU锁存器设计  

A Low Cost Double-Node-Upset Tolerant Latch Design Based on Node Redundancy Technique

作　　者：施峰 张瑾[1] SHI Feng;ZHANG Jin(Jiangsu Open University)

机构地区：[1]江苏开放大学

出　　处：《中国集成电路》2025年第3期50-54,共5页China lntegrated Circuit

摘　　要：随着集成电路特征尺寸不断缩减,软错误逐渐成为影响集成电路可靠性的主要威胁因素。针对这种情况,本文提出了一种基于节点冗余技术的低功耗容忍DNU锁存器设计(DNUTL)。该锁存器使用由四对反相器构成的存储单元保证数据稳定锁存,另外采用时钟钟控和快速通路技术有效降低了锁存器的功耗和延迟。HSPICE仿真结果显示,在相同实验条件下,与具有相同加固性能的锁存器相比,本文提出锁存器功耗平均降低70.97%,延迟平均增加18.77%,面积平均降低14.28%,PDP平均降低70.44%。s:With the aggressive scaling in the feature size of integrated circuits,soft errors are gradually becoming a major threat factor affecting the reliability of integrated circuits.To address this situation,this paper proposes a low cost double-node-upset tolerant latch design based on node redundancy technique(DNUTL).the latch uses a storage cell composed of four pairs of inverters to ensure stable data locking.In addition,clock control and high-speed path technology are adopted to effectively reduce the power consumption and delay of the latch.HSPICE simulation results demonstrate that under the same experimental conditions,compared with latches with the same reinforcement performnce,the proposed DNUTL achieves a 70.97%reduction on average in power consumption,18.77%increase on average in delay,14.28%reduction on average in area overhead,and 70.44%reduction on average in the power-delay-product.

关 键 词：软错误 节点冗余 单粒子翻转 多节点翻转 

分 类 号：TN40[电子电信—微电子学与固体电子学]