多芯片组件功率芯片粘接失效分析及工艺改进  

Failure Analysis and Process Optimization of Power Chip Bonding Process in Multi-Chip Module

作　　者：孙鑫 金家富[1] 闵志先[1] 吴伟[1] 张建 何威 SUN Xin;JIN Jiafu;MIN Zhixian;WU Wei;ZHANG Jian;HE Wei(Aperture Array and Space Exploration Laboratory of Anhui Province,The 38th Research Institute of CETC,Hefei 230088,China)

机构地区：[1]中国电子科技集团公司第三十八研究所孔径阵列与空间探测安徽省实验室,合肥230088

出　　处：《电子工艺技术》2025年第2期15-18,共4页Electronics Process Technology

基　　金：科技基础加强计划项目。

摘　　要：在微波多芯片组件中,VDMOS功率芯片常见的组装模式为粘接或焊接。导电胶粘接芯片虽具有操作简单、工艺温度低和便于返修的优点,但芯片的流片过程中易引入污染,在水、氧气条件下与背金电镀Ni层、导电胶Ag粉发生电化学腐蚀,导致接触电阻增大的失效现象。经试验分析发现,芯片背面污染无有效的去除方法,为避免污染物对电性能的影响,将粘接改为焊接后粘接,即芯片先焊接到钼铜载体上,检查钎透率合格后再用导电胶粘接到基板上,芯片漏极背金层熔解到焊料中形成稳定的冶金结合,原有污染界面将不复存在,可有效提升芯片连接的可靠性。Electrically conductive adhesive(ECA)bonding and eutectic soldering are common assembly modes for VDMOS power chip in microwave multi-chip modules.The ECA bonding mode has the advantages of simple operation,low process temperature and easy to repair,but the bonding reliability has become one of the difficulties in its application.The backside metallization layer of chip is easy to be polluted in the tapeout process.Under the condition of water,oxygen and pollutants,electrochemical corrosion reactions occur with the Ni in the backside metallization layer and the Ag in the ECA due to the potential difference,which leads to an increase in contact resistance.The analysis shows that there is no effective method for removing pollutants.In order to improve the stability of electrical properties,the bonding process can be changed to eutectic soldering process,that is,the chip is combined with the Cu/Mo carrier through eutectic soldering,and then bonded to the substrate through ECA.The metallization layer melts into the solder to form a stable metallurgical bond,and the original contaminated interface disappears,which can effectively improve the reliability of the chip connection.

关 键 词：多芯片组件 VDMOS 粘接 焊接 钼铜载体 

分 类 号：TN605[电子电信—电路与系统]