应用于航空航天领域的低功耗多节点抗辐射静态随机存取存储器设计  

Low-Power Multi-Node Radiation-Hardened SRAM Design for Aerospace Applications

作　　者：柏娜[1] 李钢 许耀华[1] 王翊[1] BAI Na;LI Gang;XU Yaohua;WANG Yi(School of Integrated Circuits,Anhui University,Hefei 230601,China)

机构地区：[1]安徽大学集成电路学院,合肥230601

出　　处：《电子与信息学报》2025年第3期850-858,共9页Journal of Electronics & Information Technology

基　　金：安徽高校协同创新项目(GXXT-2022-080,GXXT-2023-015)。

摘　　要：随着对太空的探索的深入,人们发现应用于航天领域的静态随机存取存储器(SRAM)易受到高能粒子轰击发生电节点翻转(SEU)和多节点翻转(SEMNU)。该文为解决SRAM的单粒子翻转问题提出一种16TSRAM单元可以用于SRAM的抗翻转应用,该单元包含3个敏感节点,使用金属氧化物半导体(MOS)管堆叠结构,较大提高了单元的稳定性。在65 nm CMOS工艺下仿真证明该单元可以解决SEU和SEMNU问题。相比于SARP12T,LWS14T,SAR14T,RSP14T,EDP12T和SIS10T,MNRS16T的保持静态噪声容限(HSNM)分别提升了1.4%,54.9%,58.9%,0.7%,59.1%和107.4%。相比于SARP12T,RH12T,SAR14T,RSP14T,S8N8P16T,EDP12T和SIS10T,MNRS16T的读取静态噪声容限(RSNM)分别提升了94.3%,31.4%,90.3%,8.9%,71.5%,90.4%和90.3%。相较于SAR14T,RSP14T和EDP12T,MNRS16T的保持功率(Hpwr)降低了24.7%,33.9%和25.7%。Objective As space exploration advances,the requirement for high-density memory in spacecraft escalates.However,SRAMs employed in aerospace applications face susceptibility to Single-Event Upsets(SEUs) and Multiple-Node Upsets(MNUs) due to high-energy particle bombardment,compromising the reliability of spacecraft systems.Hence,it is essential to engineer an SRAM design characterized by superior radiation resistance,reduced power consumption,and enhanced stability,fulfilling the rigorous demands of aerospace applications.Methods This paper proposes a 16T SRAM cell,designated as MNRS16T,featuring three sensitive nodes and utilizing a MOS transistor stacking structure.In this configuration,the upper tier of the stack employs a cross-coupling technique to enhance the pull-up drive capability while simultaneously diminishing that of the pull-down structure,thus balancing the driving abilities of both.The fundamental operations of the MNRS16T include write,read,and hold functions.For the write operation,bit lines WL and WWL are set to VDD,with specific MOS transistors managed to input data.During the read operation,word lines BL and BLB are precharged to VDD,and data is retrieved by assessing the voltage disparity across the bit lines.In the hold operation,bit lines are connected to ground,and word lines are precharged to VDD to preserve the data integrity.To assess the efficacy of MNRS16T,simulations are conducted using a 65nm CMOS process.Performance metrics,benchmarked against other SRAM cells include read access time,write access time,Hold Static Noise Margin(HSNM),Read Static Noise Margin(RSNM),Hold power(Hpwr),and soft error recovery capability.Results and Discussions MNRS16T exhibits superior performance across various metrics.In terms of read access time,MNRS16T exceeds other cells like SIS10T,SARP12T,and LWS14T,attributed to its efficient discharge path and optimal cell ratio(Fig.4(a)).Regarding write access time,MNRS16T outperforms most counterparts.Specifically,its write access time is reduced compared to S

关 键 词：单粒子翻转 抗辐射 静态随机存取存储器 

分 类 号：TN402[电子电信—微电子学与固体电子学]