具有超低比导通电阻的双漂移区双导通路径新型横向双扩散金属氧化物半导体  

A novel LDMOS with dual-drift region and dual-conduction path with ultra-low specific on-resistance

作　　者：段宝兴[1] 任宇壕 唐春萍 杨银堂[1] DUAN Baoxing;REN Yuhao;TANG Chunping;YANG Yintang(Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices,School of Microelectronics,Xidian University,Xi’an 710071,China)

机构地区：[1]西安电子科技大学集成电路学部,宽禁带半导体材料与器件教育部重点实验室,西安710071

出　　处：《物理学报》2025年第8期221-228,共8页Acta Physica Sinica

摘　　要：本文提出了一种具有双漂移区和双导通路径的新型横向双扩散金属氧化物半导体(LDMOS)器件,实现了超低比导通电阻(R_(on,sp)).其漂移区采用P型和N型纵向交替所构成的双漂移区结构,并引入平面栅和槽型栅分别控制P型和N型漂移区,使得器件能够在漂移区中形成两条独立的电子导通或消失路径.在对平面栅施加正向电压时,可使P型漂移区的表面发生反型,形成连接沟道和N+漏极的高浓度电子反型层,从而极大提高器件导通时的电子密度,降低比导通电阻.槽型栅极的引入可使器件在关断时产生一条额外的电子消失路径,从而缩短器件的关断时间(t_(off)).此外,由于引入P型漂移区,使得电子在P型漂移区内输运时与其体内的空穴发生复合,从而加快了电子的消失过程并进一步地缩短器件的t_(off).仿真结果表明,在200 V的击穿电压(BV)等级下,本文所提出的新型LDMOS的R_(on,sp)为3.43 mΩ·cm^(2),关断时间为9 ns.相比传统的LDMOS器件,R_(on,sp)和t_(off)分别下降了90%和11.6%.该器件不仅实现了R_(on,sp)和BV的良好折中,而且缩短了器件的t_(off),展现出了优异的器件性能.In order to improve the contradictory between specific on-resistance(R_(on,sp))and breakdown voltage(BV)of lateral double-diffused metal oxide semiconductor(LDMOS)and enhance the turn-off characteristic,this paper proposes a novel LDMOS device with dual-drift regions and dual-conduction paths,which achieves an ultra-low R_(on,sp).The key feature of the proposed device is the introduction of a dual-drift region structure with alternating P-type and N-type regions,combined with planar and trench gates to control the P-type and N-type drift regions,respectively.This configuration enables the formation of two independent electron conduction paths within the drift region.When a positive voltage is applied to the planar gate,a voltage difference is generated between the surface of the P-type drift region and the body of device’s drift.Therefore,under the influence of the voltage difference,the electrons are pulled to the surface of the P-type drift region to invert and form a high-density electron inversion layer that connects the channel and the N+drain,significantly increasing the electron density during conduction and reducing the R_(on,sp).The introduction of the trench gate provides an additional electron disappearance path,which shortens the device's turn-off time(t_(off)).Furthermore,the introduction of the P-type drift region facilitates the recombination of electrons with holes within the P-type drift region,accelerating the electron disappearance process and further reducing the device’s t_(off).Furthermore,the proposed device exhibits a more uniform electric field distribution and higher voltage capability is due to the P+N-N+P+structure adopted in the PolySi-top layer.During the off-state,both the P+N-junctions and the N+P+junctions generate electric field peaks at the interfaces.These peaks modulate the electric field distribution across the surface of the drift region.Simulation results indicate that at the BV with a level of 200V,the proposed LDMOS exhibits an R_(on,sp) of 3.43 mΩ·cm² and a t_(off

关 键 词：双漂移区 双导通路径 比导通电阻 击穿电压 

分 类 号：TN386[电子电信—物理电子学]