基于Boole过程的考虑互连延迟的逻辑电路波形模拟中的关键问题  

The Crucial Problems in Boole Process-Based and Considering Interconnecting Delay Waveform Simulation for Logic Circuit

作　　者：冯刚[1] 马光胜[1] 杜振军[1] 

机构地区：[1]哈尔滨工程大学计算机科学与技术学院,哈尔滨150001

出　　处：《计算机工程与应用》2003年第6期13-15,40,共4页Computer Engineering and Applications

基　　金：国家自然科学基金项目资助(编号:69973014)

摘　　要：论文运用Boole过程论中对逻辑电路进行描述和计算的基本思想,较好地解决了逻辑电路波形模拟中的冒险检测与消除、反馈环路处理、伪路径识别和惯性延迟冲突等关键问题。在此基础上,面向详细布线提出RC延迟与动态加载串扰相结合的互连线延迟计算方法,并将其融入到基于Boole过程的波形模拟算法中。论文充实和完善了基于Boole过程的波形模拟算法,改进了其中的不足之处,扩展了Boole过程的应用。Using the basic ideas that describe and compute logic circuits in Boole Process Theory,this paper settles some crucial problems in waveform simulation for logic circuit,such as hazards finding and eliminating,feedback circle treatment ,false paths discerning and inertia delay conflict.Based on these,this paper presents the method of computing interconnecting delay by combining RC delay and loading crosstalk dynamically for detailed routing,and syncretizes it into the Boole process-based waveform simulation algorithm.The methods and algorithms in this paper enrich and per-fect the Boole Process-based waveform simulation algorithm,they improve on the disadvantages in primary algorithm and extend the application of Boole Process.

关 键 词：Boole过程 互连延迟 波形模拟 惯性延迟 耦合电容 逻辑电路 超深亚微米工艺 

分 类 号：TN791[电子电信—电路与系统] TP331.1[自动化与计算机技术—计算机系统结构]