一种低功耗BIST测试产生器方案  

A Distributed BIST control scheme for Complex

作　　者：何蓉晖[1] 李晓维[1] 宫云战[1] 

机构地区：[1]中国科学院计算技术研究所,北京100080

出　　处：《微电子学与计算机》2003年第2期36-39,共4页Microelectronics & Computer

基　　金：国家自然科学基金重点项目(90207002);北京市重点科技项目(H020120120130)

摘　　要：低功耗设计呼唤低功耗的测试策略。文章提出了一种在不损失固定型故障覆盖率的前提下降低测试功耗的内建自测试测试产生器方案,该方案在原始线性反馈移位寄存器的基础上添加简单的控制逻辑,对LFSR的输出和时钟进行调整,从而得到了准单输入跳变的测试向量集,使得待测电路的平均功耗大大降低。给出了以ISCAS’85/89部分基准电路为对象的实验结果,电路的平均测试功耗降幅在54.4%～98.0%之间,证明了该方案的有效性。Low power design quests for low power testing scheme.This paper considers a BIST(built-in self-test)TPG(test pattern generator)which can reduce the power consumption during test without losing stuck-at fault coverage.By adding simple control logic on original LFSR(liner feedback shift regis-ter),both the clock and the outputs of LFSR are modified,and pseudo-SIC(single input change)test set is so gained,which highly reduces the average power consumption of CUT.Experi-mental results based on the ISCAS'85and89benchmark cir-cuits are reported,54.4%to98.0%of the original average power consumption is reduced,showing that this scheme is effective.

关 键 词：BIST 低功耗设计 内建自测试 测试产生器 线性反馈移位寄存器 集成电路 

分 类 号：TN407[电子电信—微电子学与固体电子学]