1.25 Gbps并串转换CMOS集成电路  

1.25 Gbps Serializer CMOS IC

作　　者：赵文虎[1] 王志功[1] 吴微[1] 朱恩[1] 

机构地区：[1]东南大学射频与光电集成电路研究所暨东南大学-华邦电子联合研究中心,南京210096

出　　处：《固体电子学研究与进展》2003年第1期73-78,共6页Research & Progress of SSE

基　　金：国家 8 63高技术计划 (2 0 0 1AA12 10 74) ;国家杰出青年科学基金 (6982 5 10 1)资助

摘　　要：分析了由超高速易重用单元构造的树型和串行组合结构 ,实现了在输入半速率时钟条件下 1 0路到1路吉比特率并串转换。通过理论推导着重讨论了器件延时和时钟畸变对并串转换的影响 ,指出了解决途径。芯片基于 0 .3 5μm CMOS工艺 ,采用全定制设计 ,芯片面积为 2 4.1 9mm2 。串行数据输出的最高工作速率达到 1 .62 Gbps,可满足不同吉比特率通信系统的要求。在 1 .2 5 Gbps标准速率 ,工作电压 3 .3 V,负载为 5 0 Ω的条件下 ,功耗为 1 74.84m W,输出电压峰 -峰值可达到 2 .42 V,占空比为 49% ,抖动为 3 5 ps rms。测试结果和模拟结果一致 ,表明所设计的电路结构在性能、速度、功耗和面积优化方面的先进性。文中设计的芯片具有广泛应用和产业化前景。This paper analyzed a serializer structure in two-stage cascade MUX including a tree structure and two serial structures to achieve the 10∶1 multiplexing at the bit rate of 1.25 Gbps. This IC uses high speed units but operates at the half speed of the bit rate to improve the design efficiency and to realize low power consumption. It has been developed using 0.35 μm CMOS technology and the layout was designed in full custom method. The chip was realized through a foundry technology and measured on wafer. The chip size is 24.19 mm 2 and consumes 174.84 mW under a 3.3 V supply. The measured voltage is 2.42 V p-p based on 50 Ω load, the duty cycle is 49% and the phase jitter is 35 ps rms at the 1.25 Gbps standard bit rate. The highest speed of serial data is 1.62 Gbps.

关 键 词：CMOS 吉比特以太网 并串转换 互补金属氧化物半导体工艺 集成电路 

分 类 号：TN432[电子电信—微电子学与固体电子学]