PLD设计中多路复用器的实现方法  

Realized Ways of Time Division Multiplexer in PLD Design

作　　者：熊国海[1] 万钧力[1] 袁兆强[1] 

机构地区：[1]三峡大学电气信息学院,湖北宜昌443002

出　　处：《电气电子教学学报》2003年第1期57-59,共3页Journal of Electrical and Electronic Education

摘　　要：从三个方面讨论了 PLD设计中多路复用器的实现方法 ,说明了每种方法的特点。第一种实现方法的特点是针对 F LEX系列器件结构在查找表结构的基础上 ,对工作速度和占芯片面积进行优化。第二种是用 VHDL语言描述来实现 ,其特点是抽象描述能力强 ,覆盖面广 ,当电路变得复杂时 ,相对第一种方法要简单一些。第三种方法是使用 MAX+PL US 软件中提供的宏模块 ,这种方法最简单、实用于各类器件 ,易于掌握。这三种方法在 PLThis paper makes a attempt to discuss the realized ways of time division multiplexer in PLD design from three aspects and the characters of each method are illustrated. The characters of method one is that on the basis of looking table structure in the FLEX series devices, speed and chip area are optimized. The second is that using VHDL language to set examples. The characters of language description are strong expressive ability and abstract ability, therfore when the circuit becomes complexity, it is much easier to implement than method one. The third is that using modules of macro offered by MAX+PLUSⅡ software, this method is the simplest and it is suitable for all kinds of devices and it is easier to be masteredalso. These three methods are of representation to some extent in PLD design.

关 键 词：多路复用器 PLD 宏模块 VHDL CPLD 

分 类 号：TN791[电子电信—电路与系统]