一种新颖的集成电路版图验证方法  

A New Method for Layout Verification of Integrated Circuits

作　　者：汤炜[1] 林争辉[1] 朱以南[1] 肖世红[1] 

机构地区：[1]上海交通大学大规模集成电路研究所,上海200030

出　　处：《微电子学》2003年第2期113-117,共5页Microelectronics

摘　　要：　版图验证是集成电路设计的瓶颈之一。文章全面系统地阐述了超大规模集成电路LVS版图验证的原理、方法和基本的流程,着重介绍了基于Dracula开发的CMOS、Bipolar和ABCD(AdvancedBipolarCMOSDMOS)工艺的LVS命令文件,在解决以上工艺的电路LVS的过程中,取得了令人满意的效果。Methods for layout verification of LVS of VLSI's are described in detail Its principle and basic flow are presented A set of LVS rule files for CMOS, Bipolar and advanced bipolar CMOS DMOS (ABCD) has been developed in Dracula language These files have been used in layout verifications of LVS based on CMOS, Bipolar and ABCD processes, and satisfactory results have been achieved

关 键 词：超大规模集成电路 版图验证 VLSI Dracula语言 LDMOS LVS工具 

分 类 号：TN47[电子电信—微电子学与固体电子学]