基于嵌入式内核SOC I_(DDQ)可测试设计方法  

Design Method for I _(DDQ) Testing for Embedded-Cores-Based System-on-a-Chip

作　　者：冯建华[1] 孙义和[2] 李树国[2] 

机构地区：[1]北京大学微电子学研究所,北京100871 [2]清华大学微电子学研究所,北京100084

出　　处：《计算机研究与发展》2003年第7期1129-1134,共6页Journal of Computer Research and Development

基　　金：国家自然科学基金 ( 90 2 0 70 18) ;国防重点实验室基金 ( 5 14 3 3 0 2 0 2 )

摘　　要：由于电路门数增大和晶体管亚阈值电流升高 ,导致电路的静态漏电流不断升高 ,深亚微米工艺SOC(系统芯片 )IC在IDDQ测试的实现方面存在巨大挑战 虽然减小深亚微米工艺亚阈值漏电开发了许多方法 ,如衬底偏置和低温测试 ,但是没有解决因为SOC设计的规模增大引起漏电升高的问题 首先提出了SOC设计规模增大引起高漏电流的可测试性设计概念 然后制定了一系列适合于SOC的IDDQ可测试设计规则Since increasing number of gates as well as increased sub threshold leakage of the individual transistors result in an increased static leakage current, system on a chip (SOC) ICs in deep submicron technologies present major challenge in the implementation of I DDQ testing While methods such as substrate bias and low temperature test are adequate to reduce sub threshold leakage in deep submicron technologies, almost no solution is available to address the issue of increased leakage due to enormous size of the SOC design Firstly, a design for test concept is presented to deal with the issue of high leakage due to the large size of SOC design Secondly, some design rules are provided, which are necessary to make SOC design suitable for I DDQ testing Finally, the design methodology presented facilitates I DDQ testing by controlling power supply of the individual cores through JTAG instruction registers

关 键 词：系统芯片 SOC 内核 JTAG 可测试性设计 IDDQ测试 

分 类 号：TN407[电子电信—微电子学与固体电子学] TP206.1[自动化与计算机技术—检测技术与自动化装置]