一种低压低功耗CMOS ULSI运算放大器单元  

A Low-Voltage and Low-Power CMOS ULSI Op-Amp Cell

作　　者：王向展[1] 于奇[1] 李竞春[1] 宁宁[1] 杨谟华[1] 刘玉奎[2] 谭开洲[2] 何林[2] 严顺炳[2] 

机构地区：[1]电子科技大学微电子与固体学院,四川成都610054 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2003年第5期443-446,共4页Microelectronics

基　　金：国家自然科学基金项目(60072004);高等学校博士学科点基金(2000061402)

摘　　要：　基于新型的折叠电流镜负载PMOS差分输入级拓扑、轨至轨(Rail-to-Rail)AB类低压CMOS推挽输出级模型、低压低功耗LV/LP技术和Cadence平台的实验设计与模拟仿真,采用2μmP阱硅栅CMOS标准工艺,得到了一种具有VT=±0.7V、电源电压1.1～1.5V、静态功耗典型值330μW、75dB开环增益和945kHz单位增益带宽的LV/LP运算放大器。该器件可应用于ULSI库单元及其相关技术领域,其实践有助于CMOS低压低功耗集成电路技术的进一步发展。Based on a novel folded cascode PMOS differential input architecture, classAB low voltage CMOS output stage and special consideration for LV/LP IC design, this contribution addresses a design of opamp with single supply voltage from 11 V to 15 V The amplifier achieves an openloop gain and a unit gain bandwidth higher than 75 dB and 945 kHz, respectively, and it typically dissipates a power less than 330 μW The device was implemented in a standard 2 μm Si CMOS process with threshold voltages around ±07 V The opamp can be used as a standard cell in ULSI library and for applications to related technologies

关 键 词：低压低功耗 CMOS ULSI 运算放大器 AB类输出级 集成电路 

分 类 号：TN722.77[电子电信—电路与系统]