高速CMOS时钟数据恢复电路的设计与仿真  

The Design and Simulation of High-speed CMOS Clock and Data Recovery Circuit

作　　者：邓军勇[1] 蒋林[1] 曾泽沧[1] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《微电子学与计算机》2014年第11期56-63,68,共9页Microelectronics & Computer

基　　金：国家自然科学基金重点项目(61136002);国家自然科学基金面上项目(61272120);陕西省教育厅专项科研计划项目(2010JK817)

摘　　要：针对2.5Gb/s高速收发器采用SMIC 0.18μm CMOS工艺,设计了双环半速率时钟数据恢复电路,其中锁相环环路为时钟数据恢复电路提供16相1.25GHz、等相位间隔的参考时钟,CDR环路包括采用电流模式逻辑的前端1:2解复用电路、基于相位插值与选择的时钟恢复电路、可以消除亚稳态的超前滞后采样型鉴相器电路,以及基于精度可预置的"折半与顺序查找"相位选择算法的数字滤波器电路.采用SpectreVerilog进行数模混合仿真,结果表明电路可以正确处理2.5Gb/s差分输入数据,完成时钟恢复与数据重定时.A dual-loop half-rate clock and data recovery circuit (CDR) used in 2 .5 Gb/s high-speed transceiver is designed with SMIC 0 .18 μm CMOS technology .The phase-locked loop provides 16-phase ,1 .25 GHz reference clocks with same phase interval to CDR loop .The CDR loop consists of 1:2 demultiplexer designed in current mode logic ,clock recovery circuit with an innovative phase interpolation and selection technology ,lead-lag sampling phase detector which can eliminate meta-stable state ,and precision preseted digital filter with the phase selection algorithm of binary search and sequential search . The proposed circuit is verified with digital/analog mixed simulator SpectreVerilog and the results show that the circuit can process the 2 .5 Gb/s differential data reliably to accomplish clock recovery and data retiming .

关 键 词：时钟数据恢复 双环半速率结构 相位插值 数字滤波器 

分 类 号：TN432[电子电信—微电子学与固体电子学]