雷达数据采集与特征提取系统BIT设计与实现  

Design and Implement of BIT for Radar Data Acquisition and Feature Extraction System

作　　者：李冰[1] 王伟[1] 陈曾平[1] 

机构地区：[1]国防科技大学ATR实验室,湖南省长沙市410073

出　　处：《电子工程师》2004年第1期1-4,19,共5页Electronic Engineer

摘　　要：在现代复杂电子系统中 ,内建测试 (BIT)技术作为提高系统可维修性和可测试性的重要手段 ,日益得到普遍重视和广泛应用。文中分析了雷达数据采集与特征提取系统中可测试性设计(DFT)方法 ,提出了基于DSP +双FPGA的BIT系统实现结构。故障模拟测试结果表明 。As modern weapon systems become more and more complicated, the BIT(Built in Test) technology has increasingly become an important means to enhance the maintainability and testability of the intricate electronic system. In this paper, the method of radar data acquisition and feature extraction system's DFT(design for testability) is studied, and an architecture of BIT based on DSP +dual FPGA is proposed. The design is proved eligible by fault emulation.

关 键 词：雷达 数据采集 特征提取 BIT 内建测试 可测试性设计 FPGA DSP 

分 类 号：TN957.52[电子电信—信号与信息处理]