千兆以太网高速分接集成电路设计  

Design of High Speed DEMUX IC in Gigabit Ethernet

作　　者：沈桢[1] 朱恩[1] 赵文虎[1] 王志功[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏省南京市210096

出　　处：《电子工程师》2004年第1期8-10,共3页Electronic Engineer

摘　　要：研究了千兆以太网接收系统结构 ,在此基础上设计了千兆以太网的分接芯片 ,采用0 .2 5 μmCMOS工艺设计的千兆网分接电路实现了 1.2 5Gbit s数据的 1∶10串 并转换 ,芯片核心面积4 70 μm× 32 0 μm ,在输入摆幅为 5 0 0mV、输出负载 5 0Ω条件下 ,输出 12 5Mbit s数据峰峰值是 82 8mV ,抖动有效值为 10ps ,眼图占空比为 4 1.5 % ,输出信号上升沿为 9ps。电源为 3.3V时功耗仅为 16 1mW。Based on the researching of gigabit Ethernet demultiplexer structure, The receiver chips used for Gigabit Ethernet are designed. The gigabit Ethernet receiver chips produced by 0.25 μm CMOS process have the function of 1∶10 demultiplexing and can operate at 1.25 Gbit/s, and its core area is 470 μm×320 μm. Under the condition of 500 mV input swing and 50 Ω output load,the peak to peak voltage of 125 Mbit/s output signal is 828 mV, and the rising time is 9 ps , RMS jitter is 10 ps. The power consumption is only 161 mW with 3.3 V supply voltage.

关 键 词：千兆以太网 CMOS工艺 分接集成电路 IEEE802.3z 结构设计 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术] TN492[自动化与计算机技术—计算机科学与技术]