板上芯片固化后残余应力分布的有限元模拟  

Distribution of Residual Stress in Packaging Assemblies of Chip on Board

作　　者：黄卫东[1] 孙志国[1] 彩霞[1] 罗乐[1] 程兆年[1] 

机构地区：[1]中国科学院上海微系统与信息技术研究所,上海200050

出　　处：《Journal of Semiconductors》2003年第6期649-655,共7页半导体学报（英文版）

摘　　要：用有限元模拟研究了板上芯片固化后残余应力的分布 .在 FR4及陶瓷分别作基板的两种情况下 ,残余应力分布最显著的差异是等效应力分布不同 .讨论了基板厚度及粘合胶厚度对残余应力的影响 ,表明采用陶瓷基板时增加粘合胶的厚度以降低残余应力来作为低应力封装的一种手段是可行的 .硅压阻传感芯片测量结果与计算机模拟结果的比较表明 ,计算机模拟值与实验测量值比较接近 。The distribution of residual stress in the packaging assemblies of chip on board (COB) is investigated using FE simulations and experiments.Using FR4 and ceramic substrates,the most obvious difference of residual stress is on the distribution of equivalent stress.The simulation results show that the thickness of the substrate has an influence on residual stress only for thickness 0～1.0mm.The simulations also indicate that the thickness of adhesive has some effects only on the residual shear stress when FR4 substrate is used.But in case of ceramic substrate,the equivalent stress decreased significantly as the thickness of adhesive increased.It means that the adjustment of the thickness of adhesive could be served as a process for low stress packaging of a ceramic-based structure.The simulated results are near to the data measured by test of silicon piezoresistive sensors,and the signs (positive or negative) of the residual stress of both the simulation and measurement are also the same everywhere on the top surface of the die.

关 键 词：板上芯片 残余应力 有限元模拟 硅压阻传感器 

分 类 号：TN305.94[电子电信—物理电子学]