万兆以太网物理层全集成单片锁相环电路  

Completely Integrated PLL for 10-gigabit Ethernet

作　　者：孟凡生[1] 朱恩[1] 孙玲[1] 费瑞霞[1] 吴春红[1] 王志功[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《光电子技术》2004年第1期32-35,50,共5页Optoelectronic Technology

基　　金：国家 8 63计划资助项目 ( No.2 0 0 1 AA1 2 1 0 74)

摘　　要：给出了一个采用 0 .2μm Ga As PHEMT工艺实现的单片集成高速锁相环电路。芯片采用差分电感电容谐振式负跨导压控振荡器 ,总面积为 0 .9mm× 0 .7mm。采用 3.3V单电源供电 ,测得芯片总功耗为 2 83m W,输出功率约 - 1 1 d Bm,中心频率 7.2 GHz,锁定范围为± 30 0MHz。环路锁定在 7.2 GHz时 ,输出信号的峰 -峰抖动约 5 .6ps,在 5 0 k Hz频偏处的单边带相位噪声为 - 94d Bc/Hz。本锁相环电路经适当修改可应用于万兆以太网物理层 IEEE80 2 .3ae1 0 GBASE- R或 1 0 GBASE- W时钟恢复电路。Clock recovery circuit (CRC) has been the main bottle-neck to realize the transceiver of the 10-Gigabit Ethernet (10-GbE), which has the operating speed of 10 Gb/s. Phase locked loop (PLL) is the key component in the CRC. A 7.2 GHz fully integrated single chip PLL designed in 0.2 μm GaAs PHEMT technology has been realized and characterized. The chip size is 0.9×0.7 mm 2 with a differential negative-G m LC-VCO. The power consumption is 283 mW at a supply voltage of 3.3 V. The output power is about -11 dBm. The locking range is approximately ±300 MHz with a center frequency of 7.2 GHz. The peak-to-peak jitter is about 5.6 ps and the phase noise is -94 dBc/Hz at 50 kHz offset from the carrier frequency. This PLL can be adopted in the clock recovery circuits of IEEE802.3ae type 10GBASE-R or 10GBASE-W after appropriate modification.

关 键 词：万兆以太网 物理层 锁相环 GAAS PHEMT工艺 

分 类 号：TP393.11[自动化与计算机技术—计算机应用技术] TN911.8[自动化与计算机技术—计算机科学与技术]