TDM系统高速CMOS单片集成复用/解复用器的研究  

Study of CMOS Multiplexers and Demultiplexers for TDM Communications Systems

作　　者：赵文虎[1] 王志功[1] 沈桢[1] 朱恩[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096

出　　处：《电子学报》2004年第5期825-829,共5页Acta Electronica Sinica

基　　金：国家 8 63高技术计划 (No.2 0 0 1AA1 2 1 0 74);国家杰出青年科学基金 (No.6982 51 0 1 )

摘　　要：本文分析了TDM系统中复用器和解复用器的电路结构 ,通过比较各种结构之间的优缺点和应用特点 ,提出了 10Gb/s速率工作的复用和解复用器结构及其内部所应采用的电路 .进而 ,本文着重研究了系统中关键的同步电路 ,给出了具体的设计和优化方法 .采用TSMC 0 .2 5 μmCMOS工艺 ,本文制作了四种不同的同步触发器并对其性能进行了比较 ,其中双预充电TSPC触发器可工作在 4GHz .以此为基础 ,本文还设计了半静态结构工作在 1.2 5Gb/s速率的 10 :1复用器、1∶10解复用器以及TSPC结构工作在 1.5 6 2 5Gb/s速率的 5∶1复用器和CML结构工作在 10Gb/s速率的1∶4解复用器 ,通过在晶片测试 ,其结果表明电路功能正确、工作稳定 ,达到了设计要求 ,证明了本文提出的设计方法的可行性和正确性 .The structures of multiplexers and demultiplexers in TDM communication systems are studied and a structure for 10 Gb/s transmission is proposed. To analyze the key circuits in the multiplexers and demultiplexers, four flip-flop circuits using the TSMC 0.25 μm CMOS process have been realized. These chips operate at different frequencies. Among them, the double-pre-charge TSPC circuit can operate up to 4 GHz. Further, based on the performance of the flip-flop circuits, a CMOS logic 10:1 multiplexer and 1:10 demultiplexer, a TSPC 5:1 multiplexer and a CML 1:4 demultiplexer have been fabricated. Tested on wafer, the CMOS logic multiplexer and demultiplexer operated at the bit rate of 1.25 Gb/s and the TSPC multiplexer operated up to 1.5625 Gb/s and the CML demultiplexer operated up to 12.5 Gb/s. The test results demonstrate the proposed design is suitable for the high-speed multiplexers and demultiplexers.

关 键 词：复用器 解复用器 CMOS工艺 集成电路 

分 类 号：TN929[电子电信—通信与信息系统]