一种采用半速率时钟的1.25Gbit/s串行数据接收器的设计  

A 1.25Gbit/s serial data receiver using half-data-rate clock

作　　者：郭淦[1] 叶菁华[1] 黄林[1] 陈一辉[1] 苏彦锋[1] 洪志良[1] 

机构地区：[1]复旦大学集成电路设计实验室,上海200433

出　　处：《通信学报》2004年第5期101-108,共8页Journal on Communications

摘　　要：介绍了一种用于接收1.25Gbit/s不归零随机数据的吉比特以太网接收器的设计。该电路采用半速率时钟结构,目的是为了以较低的功耗和简单的结构适应高速数据流。本文介绍了电路的主要组成部分和工作原理,突出了关键模块的设计。电路采用1.8V 0.18祄 1P6M CMOS工艺,经SpectreS仿真验证以及流片测试,主要功能已经实现。An Ethernet receiver for 1.25Gbit/s NRZ data is described. This circuit works at half of the data rate, in order to be adapted with high rate data stream with low power and reduced complexity for design. The main building blocks and operation principles are introduced, and the key parts of the circuit are also described. The circuit adopts 1.8V 0.18祄 CMOS 1P6M technology. Verified with SpectreS simulator, the circuit works properly under different corners. The chip is tested, and the main function is correct.

关 键 词：以太网 时钟与数据恢复 接收器 均衡器 压控振荡器 串并转换 

分 类 号：TN45[电子电信—微电子学与固体电子学]