基于28 nm工艺的SOC芯片时钟树优化  

SOC Chip Clock Tree Optimization Based on 28 nm Process

作　　者：侯宇 王爽[1] 

机构地区：[1]天津职业技术师范大学电子工程学院,天津

出　　处：《机械工程与技术》2022年第5期507-513,共7页Mechanical Engineering and Technology

摘　　要：针对SOC芯片设计中时钟树的综合效率和时序收敛问题,提出一种高效的时钟树综合方法,特别适用于现代先进深亚微米工艺中高度集成和高复杂度的设计。传统的时钟树综合方法,通过从下到上采用分步综合的方法进行了改进。该设计方法在基于台积电28 nm工艺的CPU芯片中成功进行了流片验证,结果表明,在实现传统设计功能并完成时序收敛的前提下,逐步去综合可以减少不必要的器件插入,减小芯片面积,降低整体功耗。Aiming at the comprehensive efficiency and timing convergence of clock trees in SOC chip design, an efficient clock tree synthesis method is proposed, which is especially suitable for highly integrated and high complexity designs in modern advanced deep submicron processes. The traditional clock tree synthesis method has been improved by adopting a step-by-step synthesis method from bottom to top. The design method was successfully tested in the CPU chip based on TSMC’s 28 nm process, and the results showed that under the premise of realizing the traditional design function and completing the timing closure, the gradual de-synthesis can reduce unnecessary device insertion, reduce the chip area, and reduce the overall power consumption.

关 键 词：CPU芯片 综合效率 时钟树 芯片面积 深亚微米工艺 高度集成 复杂度 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]