ALL-DIGITAL

作品数：14被引量：10H指数：2
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相关期刊：《High Technology Letters》《Chinese Optics Letters》《Semiconductor Photonics and Technology》《Journal of Semiconductors》更多>>
相关基金：国家自然科学基金国家高技术研究发展计划国家重点基础研究发展计划更多>>
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A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits被引量：1
《Science China(Information Sciences)》2019年第6期106-121,共16页Jincheng YANG Zhao ZHANG Nan QI Liyuan LIU Jian LIU Nanjian WU 
supported by National Nature Science Foundation of China (Grant Nos. 61331003, 61474108, 61234003);National Key Technology Research and Development Program of the Ministry of Science and Technology of China (Grant No. 2016ZX03001002)
This paper proposes a synthesized injection-locked bang-bang phased-locked loop(SILBBPLL)with high digital controlled oscillator(DCO) frequency resolution. The SILBBPLL is expressed with hardware description language ...
关键词：SYNTHESIZED ALL-DIGITAL phased-locked loops(ADPLL) bang-bang phased-locked loop(BBPLL) automatically placed & routed(APR) output feedback DAC(OFDAC) INJECTION-LOCKED 
A low-power,area-efficient all-digital delay-locked loop for DDR3 SDRAM controller被引量：1
《Science China(Information Sciences)》2014年第12期172-179,共8页CHEN HongMing MA Song WANG Liu ZHANG Hao PAN KenYi CHENG YuHua 
supported by National 02 Key Special Program(Grant No.2009ZX02305-005);National Hightech R&D Program of China(863 Program)(Grant No.2013AA014102);National No.2 Special Key ProjectProgram(Grant No.2012ZX02503005)
A new low-power, area efficiency all-digital delay-locked loop （ADDLL） circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz （DDR3- 667/800/1066/1...
关键词：all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code 
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