SERDES

作品数：223被引量：161H指数：6
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相关作者：池雅庆郭阳丁浩龚广伟黄贤俊更多>>
相关机构：国防科学技术大学电子科技大学东南大学西安电子科技大学更多>>
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A 6.25 Gb/s equalizer in 0.18μm CMOS technology for high-speed SerDes被引量：1
《Journal of Semiconductors》2013年第12期115-121,共7页张明科 胡庆生 
This paper presents a 0.18μm CMOS 6.25 Gb/s equalizer for high speed backplane communication. The proposed equalizer is a combined one consisting of a one-tap feed-forward equalizer （FFE） and a two-tap half-rate de...
关键词：feed-forward equalizer （FFE） decision feedback equalizer （DFE） delay line active-inductive peak-ing current mode logic （CML） 
Design and analysis of a bang-bang PLL for 6.25 Gbps SerDes
《Journal of Semiconductors》2012年第12期73-80,共8页周明珠 
Project supported by the Zhejiang Provincial Natural Science Foundation of China(No.Y1110991);the National Natural Science Foundation of China(No.61102027);the Start Research Foundation of Hangzhou Dianzi University(No.KYS045609050)
An analysis illustrates the loop nonlinear performance in a bang-bang PLL. A third-order equivalent model is deduced to give an approximate evaluation of the loop parameters. The architecture of the proposed phase det...
关键词：PLL bang-bang PD LC VCO 
A 750 MHz semi-digital clock and data recovery circuit with 10^(-12) BER
《Journal of Semiconductors》2011年第12期139-143,共5页韦雪明 王忆文 李平 罗和平 
A semi-digital clock and data recovery （CDR） is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Imple...
关键词：clock and data recovery INTERPOLATOR SERDES 
A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture
《Journal of Semiconductors》2011年第4期145-148,共4页张小伟 胡庆生 
Project supported by the National High Technology Research and Development Program of China(No2006AA01Z239)
A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells ...
关键词：SERDES 10 B/8 B decoder PIPELINED HIGH-SPEED 
A Low Jitter Design of Ring Oscillators in 1.25GHz Serdes被引量：1
《Journal of Semiconductors》2008年第3期490-496,共7页肖磊 刘玮 杨莲兴 
A new configuration for delay cells used in voltage controlled oscillators is presented. A jitter comparison between the source-coupled differential delay cell and the proposed CMOS inverter based delay cell is given....
关键词：SERDES voltage controlled ring oscillator low jitter 
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