A new clock-driven ECO placement algorithm is pr es ented for standard-cell layout design based on the table-lookup delay model.It considers useful clock skew information in the placement stage.It also modifies the ...
Project Supported by National Natural Science Foundation of China!( No.697760 2 7) and by973 National Key Project( No.G1 9980)
An algorithm is presented for obtaining placements of cell\|based very large scale integrated circuits, subject to timing constraints based on table\|lookup model. A new timing delay model based on some delay tables o...