考虑工艺偏差的容软错误锁存器设计  

Design of Soft Error Tolerant Latch in the Presence of Process Variation

作　　者：黄正峰[1] 申思远[1] 王志[1] 

机构地区：[1]合肥工业大学电子科学与应用物理学院,合肥230009

出　　处：《微电子学与计算机》2015年第6期15-21,共7页Microelectronics & Computer

基　　金：国家自然科学基金(61106038;61274036;61371025;61474036);博士点基金(20110111120012);合肥工业大学科学研究发展基金(2013HGXJ0197)

摘　　要：随着集成电路工艺尺寸的不断降低,CMOS电路越来越容易受到单粒子效应的影响并产生软错误.为了降低电路软错误率,提出一种高可靠的容软错误锁存器.该锁存器采用分离反相器P、N管栅极的方法构建内部冗余存储节点使其对SEU完全免疫,并且进行了滤波设计使其可以屏蔽SET.HSPICE的仿真结果表明,与其他加固结构相比,该锁存器在综合考虑容错性能和开销时有明显的优势,而且受到工艺偏差和温度的影响较小.With the integrated circuit feature size decreasing,the sensitivity of CMOS circuits to single event effect is increasing and leads to soft errors.In order to reduce soft error rate of integrated circuits,a soft error tolerant robust latch is proposed.By means of separating the gate of NMOS and PMOS transistors in an inverter to build redundant storage nodes,the latch could be immune to SEU.Taking advantage of filtering pulse design,the latch can mask SET.HSPICE simulation results show that the proposed latch has advantages on fault tolerance performance and overheads comparing with the reference designs,and has less sensitive to process and temperature variation.

关 键 词：锁存器 软错误 单粒子效应 工艺偏差 

分 类 号：TN432[电子电信—微电子学与固体电子学]