自对准Ti－SALICIDE　LDD　MOS工艺研究  

Investigation of Self-Aligned Ti-Silicide LDD MOS Technology

作　　者：徐秋霞[1] 龚义元[1] 张建欣 汪锁发[1] 翦进 海潮和[1] 扈焕章[1] 

机构地区：[1]中国科学院微电子中心研究部

出　　处：《Journal of Semiconductors》1994年第9期603-610,共8页半导体学报（英文版）

摘　　要：本文着重研究了０．６μｍ自对准Ｔｉ－ＳＡＬＩＣＩＤＥＬＤＤＭＯＳ工艺技术．ＴｉＳｉ２的形成采用两步快速热退火及选择腐蚀完成，Ｔｉ膜厚度的最佳选择使ＳＡＬＩＣＩＤＥ工艺与０．２μｍ浅结相容，源／漏薄层电阻为４Ω／□．上述技术已成功地应用于０．６μｍ自对准Ｔｉ－ＳＡＬＩＣＩＤＥＬＤＤＮＭＯＳ器件及其Ｅ／ＤＭＯＳ３１级环形振荡器的研制，特性良好．Abstract In this paper the technologies for 0.6μm self-aligned Ti-Silicide LDD MOS device are investigated. Two-step rapid thermal annealing and selective etchare adopted for TiSi2 formation. The optimum of Ti thickness makes SALICIDE technology compatible with 0.2μm shallow junction depth, the sheet resistance obtained for n+ source/drain is 4.0Ω/□. The technologies mentioned above have been successfully applied to the fabrication of 0.6μm self-aligned Ti-Silicide LDD NMOSFET and E/D MOS 31 stage ring oscillators with good characteristics.

关 键 词：Ti-SALICIDE 自对准 MOS器件 工艺 

分 类 号：TN386.105[电子电信—物理电子学]