低温制备应变硅沟道MOSFET栅介质研究  

Preparation of Low-Temperature SiO_2 Gate Insulators for Strained Si-Channel Heterojunction PMOSFET's

作　　者：谭静[1] 李竞春[1] 杨谟华[1] 徐婉静[2] 张静[2] 

机构地区：[1]电子科技大学微电子与固体电子学院,四川成都610054 [2]模拟集成电路国家重点实验室中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2005年第2期118-120,124,共4页Microelectronics

基　　金：模拟集成电路国家重点实验室资助项目(51439010303DZ0202)

摘　　要：　分别对300°C下采用等离子体增强化学气相淀积(PECVD)和700°C下采用热氧化技术制备应变硅沟道MOS器件栅介质薄膜进行了研究。采用PECVD制备SiO2栅介质技术研制的应变硅沟道PMOSFET(W/L=20μm/2μm)跨导可达45mS/mm(300K),阈值电压为1.2V;在700°C下采用干湿氧结合,制得电学性能良好的栅介质薄膜,并应用于应变硅沟道PMOSFET(W/L=52μm/4.5μm)器件研制,其跨导达到20mS/mm(300K),阈值电压为0.4V。An investigation is made into preparations of thin gate-oxides for strained Si channel MOSFET's using PECVD at 300 °C and low-temperature (700-800 °C) thermal oxidation, respectively. It has been shown that strained Si-channel PMOSFET's (W/L=52 μm/4.5 μm) based on thin gate-oxides prepared by a combination of dry and wet thermal oxidation at 700 °C have a transconductance of 20 mS/mm (300 K) and a threshold voltage of 0.4 V, while strained Si-channel PMOSFET's (W/L=20 μm/2 μm) based on SiO_2 gate-insulator prepared by PECVD have a transconductance of 45 mS/mm (300 K) and a threshold voltage of 1.2 V.

关 键 词：等离子体增强化学气相淀积 低温热氧化 栅介质 应变硅沟道 MOS器件 

分 类 号：TN304.055[电子电信—物理电子学]