VLSI电路短路和开路故障模型研究进展  

A Survey of the Short and Open Fault Models for VLSI Circuits

作　　者：陈火军[1] 江建慧[1] 

机构地区：[1]同济大学计算机科学与技术系,上海200092

出　　处：《计算机工程与科学》2005年第4期49-53,共5页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(90207021);同济大学理科科技发展基金项目

摘　　要：本文概述了近十年来VLSI电路的短路和开路缺陷及其故障建模的研究进展。本文将VLSI电路短路缺陷分为逻辑门内部的短路和逻辑门之间的互连短路两大类,重点介绍了栅氧短路和桥接故障模型。相应地,文中将 VLSI电路的开路缺陷分为逻辑门内部的开路和逻辑门之间的互连开路两大类,重点介绍了逻辑门内部的网络断开、浮栅和互连开路的故障模型。文中还讨论了故障模型与测试的关系。分析结果表明,目前已有的短路和开路故障模型还不够完善,特别需要研究故障机制对电路中其它节点动态行为的依赖性和对噪声的敏感性。In this paper, the short and open fault models for MOS VLSI circuits proposed in recent years are reviewed. These fault models are classified into two classes, respectively, i.e. intra-gate shorts and inter-gate shorts, and intra-gate opens and outside gate opens. We emphasize on the models of gate oxide shorts, bridging faults, network breaks within a logic gate, the floating gate defects and interconnect open defects. The advantages and disadvantages of some fault models, and the relationship between fault models and testing are discussed. The existing results show that the well-assessed short and open fault models are not adequate for high-quality testing of deep submicron CMOS digital ICs, and new short and open fault models that consider the strong dependence of the fault mechanisms in deep submicron on the activity of other nodes in the circuit and their strong susceptibility to noise will be needed.

关 键 词：超大规模集成电路 VLSI 浮栅 短路故障 开路故障 电路版图 故障模型 

分 类 号：TN47[电子电信—微电子学与固体电子学]