基于FPGA的神经网络自整定PID控制器设计  

The Design of Neural Network Self-Tuning PID Controller Based on FPGA

作　　者：江吕锋[1] 白瑞林[1] 沈宪明[1] 

机构地区：[1]江南大学控制科学与工程研究中心,无锡214036

出　　处：《自动化仪表》2005年第5期12-14,17,共4页Process Automation Instrumentation

基　　金：江南大学基础研究基金项目 (编号 :2 0 0 2 0 8)。

摘　　要：本文基于FPGA(现场可编程门阵列)技术实现了改进的BP网络自整定PID控制器的设计。首先,采用MATLAB设计控制器,针对特定被控对象模型,在闭环控制系统中通过改进的BP网络算法训练神经网络,获得比较理想的系统输出;依据训练好的网络权值,在FPGA集成开发环境下,基于VHDL(甚高速集成电路硬件描述语言)设计BP网络自整定PID控制器,完成时序仿真测试,并在一种具体的FPGA器件上实现。实验表明,其设计过程合理,实现结果正确,适合于采用复杂智能控制策略并要求实时性、快速性的单片或小型控制系统。In this paper, an improved BP neural network self-tuning PID controller based on FPGA (Field Prog rammable Data Array) is designed. At fir st, the controller is designed in MATLAB , the neural network is trained with the improved BP algorithm based on the give n object model in the closed loop contro l system to take the perfect system outp ut. Depending on the network weights, th e BP neural network self-tuning PID cont roller based on VHDL (Very high speed in tegrated circuit Hardware Description La nguage) is designed under the FPGA integ ration development environment, then its timing simulation and its implementatio n at the FPGA device are completed. The experiment indicates that the design pro cess is reasonable and the test result i s accurate. The controller is fit to imp lement intelligent control strategy on t he real-time basis, as well as fast and single-chip or small control system.

关 键 词：神经网络 控制器设计 自整定PID控制器 高速集成电路硬件描述语言 现场可编程门阵列 MATLAB BP网络算法 闭环控制系统 集成开发环境 FPGA器件 智能控制策略 技术实现 对象模型 系统输出 网络权值 VHDL 仿真测试 设计过程 

分 类 号：TP18[自动化与计算机技术—控制理论与控制工程] TP273[自动化与计算机技术—控制科学与工程]