Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates  

薄虚拟SiGe衬底上的应变Si pMOSFETs(英文)

作　　者：李竞春[1] 谭静[1] 杨谟华[1] 张静[2] 徐婉静[2] 

机构地区：[1]电子科技大学微电子与固体电子学院,成都610054 [2]模拟集成电路国家重点实验室,重庆400060

出　　处：《Journal of Semiconductors》2005年第5期881-885,共5页半导体学报（英文版）

基　　金：模拟集成电路国家重点实验室基金资助项目(批准号:51439010303DZ0221)~~

摘　　要：Strained-Si pMOSFETs on very thin relaxed virtua l SiGe substrates are presented.The 240nm relaxed virtual Si 0.8 Ge 0.2 layer on 100nm low-temperature Si(LT-Si) is grown on Si(100) substrates by molecular beam epitaxy.LT-Si buffer layer is used to release stress of the SiGe layer so as to make it relaxed.DCXRD,AFM,and TEM measurements indicate that the strain relaxed degree of SiGe layer is 85%,RMS roughness is 1.02nm,and threading dislocation density is at most 107cm -2 .At room temperature,a maximum hole mobility of strained-Si pMOSFET is 140cm2/(V·s).Device performance is comparable to that of devices achieved on several microns thick relaxed virtual SiGe substrates.成功地试制出薄虚拟SiGe衬底上的应变Si pMOSFETs.利用分子束外延技术在100nm低温Si(LT- Si)缓冲层上生长的弛豫虚拟Si0.8Ge0.2衬底可减薄至240nm.低温Si缓冲层用于释放虚拟SiGe衬底的应力,使其应变弛豫.X射线双晶衍射和原子力显微镜测试表明:虚拟SiGe 衬底的应变弛豫度为85%,表面平均粗糙度仅为1. 02nm.在室温下,应变Si pMOSFETs的最大迁移率达到140cm2/(V·s).器件性能略优于采用几微米厚虚拟SiGe衬底的器件.

关 键 词：STRAINED-SI virtual SiGe substrates PMOSFET 

分 类 号：TN386[电子电信—物理电子学]