一种基于互补型单电子晶体管的全加器电路设计  

A Full Adder Realization with Complementary Single-Electron Transistors

作　　者：孙铁署[1] 蔡理[1] 

机构地区：[1]空军工程大学理学院

出　　处：《电子器件》2005年第2期366-369,共4页Chinese Journal of Electron Devices

基　　金：陕西省自然科学基金项目(2002F34);空军工程大学学术基金项目(2002X12)

摘　　要：基于单电子晶体管(SET)的IV特性和CMOS数字电路的设计思想,提出了一种由28个互补型SET构成的全加器电路结构。该全加器优点为:简化了“P-SET”逻辑块;通过选取一组参数使输入和输出高低电平都接近于0.02mV和0mV,电压兼容性好;延迟时间短,仅为0.24ns。SPICE宏模型仿真结果验证了它的正确性。Based on the I-V characteristics of single-electron transistor (SET) and the concepts of CMOS digital integrated circuit design, a full adder which consists of 28 complementary SETs is proposed. The full adder has the following characteristics: 'PSET' networks simplified; excellent compatibility of input and output voltages; with the selection of parameters, their high and low voltage approximating 0.02 V and 0 V; a brief time delay of 0.24 ns. The accuracy is validated by SPICE macro-model of SET.

关 键 词：单电子晶体管 互补 反相器 全加器 SPICE宏模型 

分 类 号：TN713[电子电信—电路与系统]