基于传统的CMOS工艺延伸漏极NMOS功率管研究  

Study of Extended Drain NMOS Fabricated with Conventional CMOS Technology

作　　者：浦志卫[1] 郭维[1] 

机构地区：[1]浙江大学信息与电子工程学系微电子技术与系统设计研究所,杭州310027

出　　处：《电子器件》2006年第3期647-650,共4页Chinese Journal of Electron Devices

基　　金：浙江教育厅资助(20051006)

摘　　要：延伸漏极N型MOS(EDNMOS)是基于传统低成本CMOS工艺设计制造,用N-well作为NMOS漏极漂移区,以提高其击穿电压。用二维器件模拟软件Medici[1]对该器件进行模拟分析,结果表明有效地提高了NMOS管击穿电压。实验结果表明采用这种结构能使低压CMOS工艺输出功率管耐压提高到电源电压的2.5倍,样管在5 V栅压下输出的电流可达到750 mA。作为开关管工作,对于1 000 pF容性负载,其工作电流在550 mA时,工作频率可达500 KHz。A new Extended Drain NMOSFET（EDNMOS）, fabricated in a conventional low cost CMOS technology, using N-well as its drain drift region is designed and fabricated to improve its breakdown voltage. Simulation and analysis with 2-D Devices Simulator Medici[1] is carried out and the results show that the breakdown voltage can be effectively improved. Experiments indicate that the breakdown voltage of this EDNMOS can be increased to 2.5 times of supply voltage and the driving current can reach up to 750 mA under 5 V gate-source voltage. The sample transistor can switch at 500 kHz frequency with 550 mA working current, driving a capacitive load of 1 000 pF.

关 键 词：互补MOS工艺 延伸漏极N型MOS 二维器件模拟软件 击穿电压 

分 类 号：TN303[电子电信—物理电子学] TN386.1