晶圆级芯片规模封装——微型表面贴装元器件  

A Wafer Level Chip Scale Package——MicroSMD

作　　者：杨建生[1] 

机构地区：[1]天水华天科技股份有限公司,甘肃天水741000

出　　处：《电子工业专用设备》2006年第11期50-55,共6页Equipment for Electronic Products Manufacturing

摘　　要：概述了美国国家半导体的晶圆级芯片规模封装技术——也就是微型表面贴装元器件(Mi-croSMD)。采用8I/O数、凸点节距为0.5mm封装论证此新型封装技术,该技术满足于低管脚数模拟和无线元器件。较高管脚数(多达48)产品扩展在各种范围的限定条件之内。论述了封装结构、工艺流程及封装可靠性,并阐述了板级组装工艺过程和互连可靠性。The paper outlines National Semiconductor＇s concept of wafer level chip scale package——also known i as microSMD. The new packaging technology has been demonstrated using an 8 I/O package with 0.5mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count （up to 48） are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

关 键 词：芯片规模封装 CSP组装 CSP返修 封装可靠性 晶圆级封装技术 

分 类 号：TN305.94[电子电信—物理电子学]