基于FPGA的高速FIR数字滤波器的设计  

High Speed FIR Digital Filter Design Based on FPGA

作　　者：王心焕[1] 

机构地区：[1]浙江大学信息工程学院,浙江杭州310029

出　　处：《现代电子技术》2007年第15期184-187,共4页Modern Electronics Technique

摘　　要：采用了分布式算法、Booth算法、Wallace树和超前进位加法器、进位选择加法器结构,以及流水线技术,基于FPGA进行了高速FIR数字滤波器的设计。以低通FIR数字滤波器为例,利用Matlab辅助滤波器设计并做了频谱特性的验证,在ISE软件上进行了功能仿真、时序仿真和综合,并给出了综合的电路框图、资源使用情况以及最高工作频率。通过运用多种优秀的快速算法及流水线技术,可以打破FPGA中缺乏实现乘累加运算有效结构的缺点,实现高速FIR数字滤波器的设计,使FPGA在数字信号处理方面有长足发展。Using distributed algorithm, Booth algorithm, Wallace tree and carry - look - ahead adder, carry - select adder, as well as pipelining technology,a high speed FIR digital filter design based on FPGA is presented. Let＇s take a low- pass digital FIR filter for example. The verification of the spectrum is done by Using Matlab auxiliary filter design,the functional simulation, timing simulation and synthesis is applied on ISE,and the general schematic circuit diagram,the use of resources and the maximum operating frequency are given. Through the use of a variety of excellent and fast algorithm pipeline technology, lacking of effective structure for realization of cumulative operation, the shortcomings in FPGA,can be broken, high speed FIR digital filter design can be achieved,and FPGA in the field of digital signal processing can be developed by leaps and bounds.

关 键 词：分布式算法 BOOTH算法 WALLACE树 超前进位加法器 进位选择加法器 流水线技术 ISE 

分 类 号：TN713[电子电信—电路与系统]