基于45nm技术的ULSI互连结构的温度模拟  

Temperature Simulation of ULSI Interconnects Based on 45 nm Technology

作　　者：王锡明[1] 周嘉[2] 阮刚[2] LEE H-D 

机构地区：[1]合肥学院机械系,合肥230022 [2]复旦大学专用集成电路与系统国家重点实验室微电子学系,上海201203 [3]城南国立大学电子工程系

出　　处：《微电子学》2007年第4期474-477,481,共5页Microelectronics

基　　金：中韩合作项目"Modeling and simulation of the rmal generation and dissipation in chip using Tera-level Nano CMO Stechnology with multi-level metallization"(TND100-130-131)资助

摘　　要：应用自行建立的准二维简化模型,计算了三种基于45 nm节点技术的ULSI九层低介电常数介质互连结构的温度升高。与ANSYS的分析对比表明,简化模型误差为7.7%。三种互连结构中,结构III设计具有最佳的散热能力,不仅工作时绝对温升小,而且随衬底温度和介质导热系数的温升加大也小;结构I的散热能力良好,结构III最差。对三种互连结构的尺寸分析表明,层间介质的厚度对互连系统的温升影响大,必须在电学模拟和温度模拟完成后找到一个最佳厚度值,以保证既有好的散热条件,又有利于减小RC延迟。互连结构的温升随电介质导热系数的减小呈二阶指数升高,特别当介质导热系数小于0.1 W/℃.m时,互连结构设计将会成为器件温升和系统可靠性的关键所在,引入新技术或许势在必行。Temperature rise in three 9-layered ULSI interconnects based on 45 nm technology was analyzed using self-developed compact quasi-analytic model. Compared with results from ANSYS, the error of our model reaches 7.7%. It can be concluded that, among the three structures, Structure Ⅲ, which has the lowest temperature rise and smallest temperature change with the increase of substrate temperature and the decrease of thermal conductivity kt, has the best heat transfer capability, while Structure Ⅱ the worst and Structure Ⅰ in between. Thick interlayer is the main cause of the severely rugged heat transfer conditions. To achieve good heat transfer and small RC delay, optimized interlayer thickness should be found after thermal and electrical simulation. It is revealed that temperature rise decays in second-order exponential with the decrease of kt. And new technology strategies should be needed for kt〈0. 1 W/℃·m.

关 键 词：超大规模集成电路 铜互连 温度分析 低介电常数材料 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]