基于0.5μm CMOS集成电路高低压兼容技术研究  

Study on Integrating CMOS Compatible High-voltage MOSFETs in a 0.5μm Process

作　　者：刘允[1] 赵文彬[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2007年第9期22-25,共4页Electronics & Packaging

摘　　要：将高压MOSFETs器件集成到低压CMOS数字和模拟电路中的应用越来越频繁。文章参考了Parpia提出结构,将高压NMOS、PMOS器件制作在商用3.3V/5V 0.5μmN-阱CMOS工艺中,没有增加任何工艺步骤,也没有较复杂BiCMOS工艺中用到的P-阱、P+、N+埋层,使用了PT注入。通过对设计结构的PCM测试,可以得到高压大电流的NMOS管BVdssn>23V～25V,P管击穿BVdssp>19V。同时,文章也提供了高压器件的设计思路和结果描述。There has been growing interest in developing high-voltage MOSFETs devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper, high-voltage n- and p-type MOSFETs were fabricated in a commercial 3.3V/5V 0.5μm N-well CMOS process without adding any process steps, based on the structures proposed by Parpia, et al. In the absence of a P-well, P＋ and N＋ buried layers which are available only in a more complex BiCMOS process, N-well and P-channel stop were used. High current and high-voltage transistors with breakdown voltages between 23V-35V for the NMOS transistors with different layout parameters and 19V for the PMOS transistors were achieved. This paper also presents the design considerations and characterization results for these high-voltage devices.

关 键 词：高压MOS器件 低压MOS器件 0.5μm CMOS工艺 工艺兼容技术 

分 类 号：TN705[电子电信—电路与系统]