铁电电容工艺与标准CMOS工艺兼容性研究  

Investigation of Compatibility of Ferroelectric Capacitor Fabrication Process with Standard CMOS Fabrication Process

作　　者：翟亚红[1] 李平[1] 张树人[1] 杨成韬[1] 阮爱武[1] 蔡道林[1] 欧阳帆[1] 陈彦宇[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,四川成都610054

出　　处：《压电与声光》2007年第5期609-611,614,共4页Piezoelectrics & Acoustooptics

基　　金：国家重点基础研究发展计划("九七三"计划)基金资助项目(51310z)

摘　　要：在铁电存储器制备过程中,Pb(Zr0.52Ti0.48)O3(PZT)铁电薄膜需经历多次热处理,铁电电容工艺与标准CMOS工艺的集成加工过程中可能存在交叉污染。对PZT薄膜中的铅在不同温度下的挥发量进行了测定,在温度为400℃时有0.15×10-6铅挥发。同时进一步研究了铁电工艺对底层NMOS管、PMOS管和CMOS电路性能的影响。实验结果表明:PMOS管的性能所受影响较大,PMOS管子的跨导(gm)明显降低;而NMOS管的性能所受影响较小;CMOS电路的数字逻辑功能正常。Pb（Zr0.52Ti0.48）O3 （PZT） thin film is treated repeatedly at higher temperature in the course of preparation for FRAM（Ferroelectric random access memory）, during which cross-contamination may be induced for CMOS fabrication process. Therefore, the volatility of lead from the PZT thin film at different temperature has been investigated and the lead volatility of 0. 15 × 10^-6 at 400 ℃ has been measured. Furthermore, the effect of fabrication process for ferroelectric capacitors on the CMOS devices and circuits on the same substrate has been analyzed in terms of experiment. The results show that the ferroelectric capacitor process makes the transconductance of the PMOS devices degrade obviously while NMOS devices and circuits can still work well.

关 键 词：PZT薄膜 铁电电容 热处理 铅挥发 跨导 

分 类 号：TN384[电子电信—物理电子学]