堆叠栅介质MOS器件栅极漏电流的计算模型  

Calculation of Gate Leakage Currents in MOS Transistors with Gate-Stacked Dielectrics

作　　者：杨红官[1] 朱家俊[1] 喻彪[1] 戴大康[1] 曾云[1] 

机构地区：[1]湖南大学物理与微电子科学学院,长沙410082

出　　处：《微电子学》2007年第5期636-639,643,共5页Microelectronics

基　　金：湖南省青年骨干教师资助项目(湘教通[2005]247号);湖南省自然科学基金资助项目(05JJ30115)

摘　　要：采用顺序隧穿理论和传输哈密顿方法并考虑沟道表面量子化效应,建立了高介电常数堆叠栅介质MOS器件栅极漏电流的顺序隧穿模型。利用该模型数值,研究了Si3N4/SiO2、Al2O3/SiO2、HfO2/SiO2和La2O3/SiO2四种堆叠栅介质结构MOS器件的栅极漏电流随栅极电压和等效氧化层厚度变化的关系。依据计算结果,讨论了堆叠栅介质MOS器件按比例缩小的前景。A sequential tunneling model was proposed to calculate direct tunneling gate currents through metaloxide semiconductor transistors （MOSTs） with high-k/SiOz gate dielectrics, using Bardeen＇s transfer Hamiltonian formalism and with quantum mechanical effect in inversion layers taken into consideration. Gate leakage currents in four MOSTs with different gate stack dielectrics （Si3 N4/SiO2, Al2O3/SiO2, HfO2 /SiO2 and La2O3/SiO2 ） vs. gate voltages and equivalent oxide thickness were investigated numerically. Sealing down of MOSTs with high-k/SiO2 gate dielectrics was discussed based on the calculated results.

关 键 词：直接隧穿 顺序隧穿 高介电常数栅介质 MOS器件 

分 类 号：TN386.1[电子电信—物理电子学]