VDSM集成电路互连特性及RC延迟研究  

Study on VDSM Interconnect Characteristics and RC Delay

作　　者：邝嘉[1] 黄河[1] 

机构地区：[1]华南师范大学计算机学院,广州510631

出　　处：《半导体技术》2008年第1期68-72,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60076013)

摘　　要：利用多层金属导体寄生电容模型，详细分析了不同的金属互连线参数对寄生电器的影响．并采用一个闭合公式对超深亚微米级集成电路中的RC互连延迟进行估计。结果表明，当金属导线的纵横比接近2时，线间耦舍电容对互连总电容的影响将占主导地位。在超深亚微米工艺条件下，当金属线宽和间距比例W／P的最优质值为0．5-0．6时，计算的互连延迟为最小。此外，还给出了低介电常数材料对互连线电容和延迟的影响，为超深亚微米级的集成电路设计与实现提供有益的参考。Effects of different metal interconnect parameters on the parasitical capacitance were analyzed with a multilevel metal capacitance model, and RC interconnect delay in VDSM circuit was estimated with a closed-form formula. Results show that, when the aspect ratio of the metal line approaches 2, the effect of incline coupling capacity on the total capacitance becomes dominant, while the optimal ratio of metal interconnect line width to interconnect pitch is 0.5 -0.6 in the VDSM process. Effects of low-k dielectric on the interconnect capacitance and time delay were also given, offering some beneficial reference for the VDSM IC design and implementation.

关 键 词：超深亚微米 寄生电容 互连 时间延迟 

分 类 号：TN405.97[电子电信—微电子学与固体电子学]