集成电路的互连线延迟分析  

Analysis of IC Interconnect Delay

作　　者：朱冬平[1] 黄河[1] 邝嘉[1] 

机构地区：[1]华南师范大学计算机科学学院,广州510631

出　　处：《现代计算机》2008年第3期18-22,共5页Modern Computer

摘　　要：IC制造技术先后进入亚微米、VDSM和UDSM工艺,互连线延迟关注随之逐渐增强。事实上,互连线延迟早已超过了器件延迟,使IC设计重点转移到以互连线设计为核心。在对互连延迟模型、延迟影响因素、互连线延迟优化以及互连线延迟对IC设计的影响作简要分析基础上,给出了有价值的总结。IC manufacturing technology has entered the sub-micron, VDSM and UDSM processes, interconnect delay concern then has been gradually strengthened. In fact, the interconnect delay has been delayed more than a device, so IC design has shifted the focus of interconnect design at the core. On the basis of giving a brief analysis of the interconnection delay model, delayed impact of factors, optimization of interconnect as well as interconnect delay in the impact of IC design, Finally, concludes a valuable summary.

关 键 词：互连线 延迟 UDSM 三维IC 寄生参数 

分 类 号：TN402[电子电信—微电子学与固体电子学] U491.1[交通运输工程—交通运输规划与管理]