一款雷达信号处理SOC芯片的存储器内建自测试设计  

MBIST Design for a Radar Signal Processing SOC Chip

作　　者：饶全林[1] 何春[1] 饶青[1] 刘辉华[1] 

机构地区：[1]电子科技大学电子科技研究院,四川成都610054

出　　处：《微电子学与计算机》2008年第7期95-99,共5页Microelectronics & Computer

摘　　要：内建自测试(BIST)为嵌入式存储器提供了一种有效的测试方法.详细介绍了存储器故障类型及内建自测试常用的March算法和ROM算法.在一款雷达信号处理SOC芯片中BIST被采用作为芯片内嵌RAM和ROM的可测试性设计的解决方案.利用BIST原理成功地为芯片内部5块RAM和2块ROM设计了自测试电路,并在芯片的实际测试过程中成功完成对存储器的测试并证明内嵌存储器不存在故障.The Built-In Self Test （BIST） provides a cost-effective solution in testing an embedded memory. Fault types of embedded memory and the March algorithm which is commonly used were introduced at first. In the DFT （Design For Testability） techniques used in a Radar Signal Processing SOC Chip. The BIST circuit was successfully inserted for five pieces of embedded RAM and tow pieces of embedded ROM. In the testing of the SOC chip, the MBIST circuit test the embedded memory successfully and approved that there was no fault in the memory.

关 键 词：存储器内建自测试 故障模型 MARCH算法 ROM算法 可测试性设计 

分 类 号：TN4[电子电信—微电子学与固体电子学]