等平面化SiC MESFET的研制  

Fabrication of Nearly Planarized SiC MESFETs

作　　者：杨霏[1] 陈昊[2] 潘宏菽[2] 默江辉[2] 商庆杰[2] 李亮[2] 闫锐[2] 冯震[2] 杨克武[2] 蔡树军[3] 姚素英[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072 [2]专用集成电路国家重点实验室,石家庄050051 [3]中国电子科技集团公司第十三研究所,石家庄050051

出　　处：《微纳电子技术》2008年第8期440-443,483,共5页Micronanoelectronic Technology

基　　金：国防科技重点实验室基金(9140C0607010704;0904C0607010705)

摘　　要：在原有设计以及工艺的基础上,采用了器件表面等平面化处理及侧壁钝化工艺,器件工作电压大幅度提高,截止漏电流降低约两个数量级,跨导提高1.5mS/mm。2GHz下测试,微波功率附加效率提高10%左右,增益平均提高了2dB,在VDS=60V的条件下单管功率输出达到了86.5W。经过内匹配和功率合成研制成大功率的SiC脉冲功率管的综合性能较好,在250W的输出功率下,器件仍然保持高达10.5dB的高增益,功率附加效率30%。台阶仪和扫描电镜观测表明,台阶高度已经大大降低,侧壁得到了钝化,尖锐突起和凹坑都已经变得平缓。New structure silicon carbide （SIC） MESFET chips with surface planarized and sidewall passivated were fabricated on the base of original design. DC characters were improved obviously. The reverse breakdown voltage increased from about 70 V to about 120 V and the leakage current decreased to about 1 mA, which was about 1 percent to the contrast. Tested at 2 GHz, the microwave output power of the chips with the new structure achieved 86.5 W while the trans- conductance increased 1. 5 mS/mm and the power gain increased 2dB. That the devices could work at much higher reverse voltage with the sharply decreased leakage current resulted in the increasing, about 10%, of power added-efficiency （PAE）. Internally-matched high power device with four chips yielded an output power more than 250W with 10.5 dB power gain and more than 30% PAE at 2 GHz. SEM and stepper characterization showed that the surface was planarized, the height of step decreased, and the sidewall was passivated with insolating media. That may be the reason of the extremely low reverse leakage current and high breakdown voltage.

关 键 词：碳化硅(SIC) 金属消特基势垒场效应晶体管 高增益 功率附加效率 大功率 等平面化 侧壁钝化 

分 类 号：TN386.3[电子电信—物理电子学] TN304.24