基于FPGA的神经网络硬件可重构实现  

Reconfigurable Hardware Realization of Neural Network Based on FPGA

作　　者：李利歌[1] 阎保定[1] 侯忠[1] 

机构地区：[1]河南科技大学电子信息工程学院,河南洛阳471003

出　　处：《河南科技大学学报（自然科学版）》2009年第1期37-40,共4页Journal of Henan University of Science And Technology:Natural Science

基　　金：河南省教育厅自然科学基金项目(200610464031)

摘　　要：针对软件实现神经网络速度慢的缺点,介绍了一种神经网络在FPGA上可重构实现的设计方法。设计中依据成熟的BP算法公式,以一个三层的BP网络为例,利用Verilog HDL硬件语言自顶向下设计各个模块,使网络训练时将前向模块、误差反传模块和相应的控制模块同时配置到FPGA中进行网络训练;而当训练好的网络正常工作时,只在FPGA中配置前向模块和相应的控制模块就可以高速运行该神经网络。实验结果表明,该系统结构能极大地提高BP网络的学习速度。Arming at the shortcoming that the speed of the realization of neural network by software is slow,this paper introduces a kind of method to reconfigurate neural network by using FPGA.Based on the mature BP algorithm formula,for a three-layer network of BP as an example,all needed sub-module are constructed from top to bottom in Verilog HDL.In the model training-process,the forward module,backward model and related control models are configured to the FPGA chip.While in the implement-process,only the forward model and related control models are needed to reconfigure onto the FPGA chip.Experiment results show that this system can improve the study speed of the BP algorithm.

关 键 词：神经网络 FPGA 可重构 VERILOG HDL 

分 类 号：TP183[自动化与计算机技术—控制理论与控制工程]