AVS解码器中码流分割模块的硬件实现  

Hardware Implementation of Code Stream Segmentation Module in AVS Decoder

作　　者：李德斌[1] 易清明[1] 石敏[1] 

机构地区：[1]暨南大学电子工程系,广东广州510632

出　　处：《电视技术》2009年第11期35-37,73,共4页Video Engineering

基　　金：广州市科技计划攻关项目(2007Z3-D3101);珠海市产学研项目(PC20082002)

摘　　要：提出一种基于AVS标准码流分割模块的硬件设计方案。简要介绍了码流分割模块的功能,根据码流特点进行硬件结构划分并重点阐述具体的硬件实现过程。采用Verilog HDL语言进行设计和仿真,实现了码流的正确解析,并与解码器其他模块结合通过了FPGA验证。仿真结果表明,整个硬件系统结构能在80MHz时钟频率下完成30f/s(帧/秒)码流的实时解码。A hardware implementation of code stream segmentation module based on AVS standard is proposed in the paper. The function of code stream segmentation module is briefly introduced, according to the characteristics of the code stream, the module is separated into several parts and hardware implementation process is mainly described. The design and simulation are conducted with Verilog HDL. The code stream is correctly parsed. Combined with other modules of decoder, the system is validated on FPGA. The simulation result shows that the whole hardware system can obtain real-time decoding with 30 frames per second at the clock frequency of 85 MHz.

关 键 词：码流分割 AVS 解码器 VERILOG HDL 

分 类 号：TN919.8[电子电信—通信与信息系统]