8位CMOS双通道流水线ADC仿真设计  

Simulation and Design of 8 bit CMOS Two-Channel Pipeline ADC

作　　者：吴衍[1] 成立[1] 王鹏程[1] 杨宁[1] 王改[1] 王振宇[1] 

机构地区：[1]江苏大学电气与信息工程学院,江苏镇江212013

出　　处：《半导体技术》2010年第1期14-17,共4页Semiconductor Technology

基　　金：国家863计划资助项目(2006AA10Z258)

摘　　要：设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。A 1.2 V 8 bit 1 GS/s two-channel pipeline ADC was designed. The designed ADC was with improved pipeline structure of two-channel 1.5 bit multiplying DAC （MDAC）. Two pipelines shared the operation amplifier and flash ADC to simplify the structure and improve the sampling speed; In order to solve time-skew and time mismatch between two channels, dedicated switch-linearization control circuits （SLC） driven by a single clock phase was designed in the front-end sample-and-hold circuits. The pipeline ADC was designed with 90 nm CMOS process. The simulated results show that the SNR is 32.7 dB, the SFDR is 42.3 dB under the usual temperature. The ADC achieves 8 resolution, 23 mW power-dissipation and 1 GS/s sampling speed. So it is suitable for high-speed, high-resolution and low power-dissipation applications.

关 键 词：双通道 CMOS工艺 流水线A/D转换器 高采样速率 低功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学]