高k栅介质/金属栅结构CMOS器件的等效氧化层厚度控制技术  

The Technology of EOT Control in High k Dielectric/metal Gate Electrode CMOS Device

作　　者：陈世杰[1] 王文武[1] 蔡雪梅[1] 陈大鹏[1] 王晓磊[1] 韩锴[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《电子工业专用设备》2010年第3期11-16,共6页Equipment for Electronic Products Manufacturing

摘　　要：随着CMOS器件特征尺寸的不断缩小,绝缘栅介质层也按照等比例缩小的原则变得越来越薄,由此而产生的栅漏电流增大和可靠性降低等问题变得越来越严重。传统的SiO2栅介质材料已不能满足CMOS器件进一步缩小的需要,而利用高介电常数栅介质(高k)取代SiO2已成为必然趋势。综述了国内外对纳米尺度CMOS器件高k栅介质的等效氧化层厚度(EOT)控制技术的一些最新研究成果,并结合作者自身的工作介绍了EOT缩小的动因、方法和展望。With CMOS device characteristic dimension scaling, the gate dielectric becomes thinner and thinner according to the principle of scaling. Consequently, the gate leakage current increases significantly and the device becomes less reliable. So the traditional SiO2 dielectric can not satisfy the next generation process node. The high k dielectric will definitely replace SiO2 as the gate dielectric. In this paper, the most recent research around world in the control of EOT （Equivalent？Oxide Thick- ness） in nano-scale CMOS high k dielectric is investigated. The reasons why to decrease EOT, the methods how to decrease it are discussed referring to the author＇s research. In the end, this paper forecasts the technology of control of EOT in high k dielectric/metal gate electrode COMS device.

关 键 词：高K栅介质 等效氧化层厚度(EOT) 金属栅 氧吸除 

分 类 号：TN405[电子电信—微电子学与固体电子学]